Conventionally, the following method of manufacturing a MOS transistor on a semiconductor substrate is generally used. First, an isolation region is formed on the semiconductor substrate using a field-forming insulation film as a mask. The field-forming insulation film is then detached to expose the active region, and a conductive film is deposited on the exposed region. The conductive film is patterned to form a gate electrode. A sidewall is formed on a side surface of the gate electrode, and a contact plug to be connected to a source/drain diffusion region is formed, thereby completing the MOS transistor.
However, according to the conventional method, three mask patterns are necessary including a mask pattern to form a field-forming insulation film (an active field pattern), a mask pattern'to form a gate electrode (a gate electrode pattern), and a mask pattern to form a contact plug (a diffusion contact pattern). A part of these three mask patterns cannot be omitted. Therefore, manufacturing cost cannot be reduced by reducing steps of manufacturing process. Furthermore, a positional mismatch between the contact plug and the active region needs to be considered at the time of forming the contact plug using the mask pattern (the diffusion layer contact pattern). Consequently, a wide active region needs to be secured by taking into account a margin for forming the contact plug, and it is difficult to reduce the area of the active region.
Furthermore, in order to form a lightly doped drain (LDD) region and a self-aligned contact, a cap insulation film is necessary on the gate electrode. In this case, a total film thickness of films including the gate electrode becomes about two times the thickness of the gate electrode, which results in a very high aspect ratio. Consequently, a processing margin becomes short in patterning the gate electrode. A margin of burying various kinds of materials in a space between gate electrodes such as a sidewall and a contact plug, and a processing margin of an interlayer insulation film that is once buried into a space between the gate electrodes and then removed become short. This problem is particularly evident in a transistor having a large film thickness of a gate electrode and a very small distance between the gate electrodes due to the employment of a polymetal structure such as a memory cell transistor of a dynamic random access memory (DRAM).
The problem of the very high aspect ratio can be solved somewhat by using a damascene process in the manufacturing of a memory cell of the DRAM, as described in Japanese patent application laid open No. 2002-43544 and Japanese patent application laid open No. 2002-110930. According to the damascene process, an inter-gate insulation film is formed before the gate electrode. Therefore, a defect due to a shortage in a covering rate of the inter-gate insulation film (a short-circuiting between contacts) can be prevented. However, in this case, it is difficult to substantially reduce steps of the photolithography process or substantially reduce the active region.
When a transistor size becomes small due to miniaturization of the transistor, a sub-threshold current increases based on what is called the “short-channel effect”. Accordingly, a refresh characteristic reduces in the DRAM, for example. In order to solve this problem, it is effective to secure a sufficient gate length while suppressing the area per one transistor by burying a gate electrode within a trench formed on a semiconductor substrate (see Japanese patent No. 3,150,496).
However, in order to embed a gate electrode into the trench, a mask pattern to form the trench on the semiconductor substrate is separately necessary. Therefore, it is also difficult to reduce steps of a photolithography process and to substantially reduce an active region.